The widespread proliferation of computers and electronic devices is continually increasing as computers are consistently being used for different and more sophisticated applications. For example, the growth and use of digital media (e.g., digital audio, video, images, and the like) has expanded the use of computers, as well as the volume and complexity of functionality needed to be supported by these devices. Likewise, new and improved electronic devices (e.g., digital audio players, video players) are continually being developed and are placing new and ever increasing demands on the technology behind these devices. This growth and development has vastly increased the processing and storage needs for computer and electronic devices, as well as the desire to produce these devices in a manner that allows such devices to be made available to consumers at affordable prices.
Accordingly, in the semiconductor industry, there is a continuing trend toward higher densities, throughput and yield. To achieve high densities, there has been and continues to be efforts toward scaling down dimensions (e.g., at submicron levels) on semiconductor wafers, which are generally produced from bulk silicon. In order to accomplish such high packing densities, smaller feature sizes and more precise feature shapes are required in integrated circuits (ICs) fabricated on small rectangular portions of the wafer, commonly known as dies. This may include the width and spacing of interconnecting lines, spacing and diameter of contact holes, as well as the surface geometry of various other features (e.g., corners and edges). The dimensions of features and the spacing therebetween can be referred to as critical dimensions (CDs). Reducing CDs, and reproducing more accurate CDs facilitates achieving higher densities through scaled down dimensions and increased packing densities. To increase throughput, the number of required processing steps can be reduced and/or the time required to perform those processing steps can be reduced. To increase yield, which is the percentage of finished products that leave a fabrication process as compared to the volume of raw materials that enter the fabrication process, quality control over individual fabrication processes can be improved.
In semiconductor fabrication a wafer is entered into a processing chamber and exits from the chamber with hundreds of copies (or more) of one or more features formed onto the wafer, and more particularly onto respective die of the wafer. During the fabrication process the wafer may be subjected to hundreds of steps that may include, for example, layering, doping, heat treating, patterning, deposition, growth, alignment, illumination, exposure, magnification/de-magnification, focusing, baking, developing, etching, patterning, implanting, polishing, reacting, and others, by which one or more transistors and/or other electrical devices are formed and interconnected on die on the wafer.
By way of example, multiple iterations of manipulating thin films may be performed to create several patterned layers on and into a substrate of the wafer. Layering is an operation that adds thin layers to the wafer surface. Layers can be, for example, insulators, semiconductors and/or conductors and are grown or deposited via a variety of processes. Common deposition techniques include, for example, CVD, sputtering and/or electroplating. Doping is another operation wherein a specific amount of dopants are selectively added to the wafer. The dopants can cause the properties of layers to be modified (e.g., change a semiconductor to a conductor). A number of techniques, such as thermal diffusion and ion implantation can be employed for doping. Heat treatments are another basic operation in which a wafer is heated and cooled to achieve specific results. Typically, in heat treatment operations, no additional material is added or removed from the wafer, although contaminants and vapors may evaporate from the wafer. One common heat treatment is annealing, which activated dopants and repairs damage to the crystal structure of a wafer/device generally caused by doping operations. Other heat treatments, such as alloying and driving of solvents, are also employed in semiconductor fabrication.
By performing these steps, the fabrication process selectively forms desired structures or features at specific locations in and on die of the wafer. These structures or features may comprise, for example, electrically active regions of integrated circuits formed on the wafer. The layer to layer orientation or registration, size, location, shape and isolation of such electrically active structures affects the reliability and performance of resulting integrated circuits employing such structures. For example, registration error, mis-alignment, mis-patterning, or other pattern anomalies that can result from process drift or other undesirable processing conditions can compromise the performance of the structures and adversely affect resulting chip performance and reliability.